Principal DFT (Design for Testability) Engineer

We are looking for an experienced lead DFT design engineer to join our ASIC design team. As lead DFT engineer you will be responsible for working closely with our Test Engineering group, design engineers, and back-end design team to define, implement, and test the DFT logic and test vectors for our next generation ASIC. This position requires that you are current with the latest DFT techniques and tools and that you have significant experience architecting and implementing all of the following in one or more successful ASIC devices:

• At-Speed Full-chip Scan, Test Compression, BIST
• Boundary Scan
• Memory BIST
• Working with multiple clock domains, including multiple PLL's
• Test vector generation, and conversion
• Fault grading
• Design rule checking

The selected candidate must have a solid understanding of the principles of DFT such that you can guide and influence the company in using the best, cost effective DFT techniques for our application.

A minimum of 8+ years DFT design experience is required.

All applicants must have excellent written and verbal communications skills, a positive attitude, a strong commitment to excellence, and a dedication to getting the job done. The selected candidate will be a self-starter, quick learner, poses a willingness and desire to take ownership of his or her work, and demonstrate the ability and desire to work with, and lead others, in a small, closely knit team.

If you are interested in this position, please E-mail your resume to: careers@pulselink.net or fax it to: 760.607.0861

Pulse~LINK is a privately held corporation headquartered in Carlsbad, California, with approximately 85 employees.